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PRELIMINARY
CY7C4282 CY7C4292
64K/128K x9 Deep Sync FIFOs w/ Retransmit & Depth Expansion
Features
* High-speed, low-power, first-in first-out (FIFO) memories * 64k x 9 (CY7C4282) * 128k x 9 (CY7C4292) * 0.5 micron CMOS for optimum speed/power * High-speed, Near Zero Latency (True Dual-Ported Memory Cell), 100-MHz operation (10 ns read/write cycle times) * Low power -- ICC=40 mA * * * * * * * * * * -- ISB = 2 mA Fully asynchronous and simultaneous read and write operation Empty, Full, and Programmable Almost Empty and Almost Full status flags TTL compatible Retransmit function Output Enable (OE) pin Independent read and write enable pins Supports free-running 50% duty cycle clock inputs Width Expansion Capability Depth Expansion Capability through token-passing scheme (no external logic required) 64-pin 10x10 STQFP The CY7C4282/92 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. All devices are 9 bits wide. The CY7C4282/92 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free-running clock (WCLK) and a write-enable pin (WEN). Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (XI), cascade output (XO), and First Load (FL) pins. The XO pin is connected to the XI pin of the next device, and the XO pin of the last device should be connected to the XI pin of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C4282/92 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable.
Functional Description
D0 -
8
Logic Block Diagram
INPUT REGISTER
WCLK WEN FLAG PROGRAM REGISTER WRITE CONTROL FF FLAG LOGIC Dual Port RAM Array 64K x 9 128K x 9 READ POINTER EF PAE PAF/XO
WRITE POINTER
RS
RESET LOGIC
FL/RT XI/LD PAF/XO EXPANSION LOGIC
THREE-STATE OUTPUT REGISTER OE Q0 -
8
READ CONTROL
RCLK REN
4282-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 September 5, 1997 - Revised November 6, 1997
PRELIMINARY
Pin Configuration
WCLK XI/LD GND N/C N/C N/C N/C N/C VCC N/C N/C Q8 Q7 GND Q6 N/C
CY7C4282 CY7C4292
STQFP Top View
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
WEN RS D8 D7 D6 N/C N/C N/C N/C N/C N/C N/C D5 D4 D3 D2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CY7C4282 CY7C4292
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Q5 Q4 GND Q3 Q2 VCC Q1 Q0 GND N/C FF EF OE GND FL/RT N/C
4282-2
Functional Description (continued)
The CY7C4282/92 provides four status pins: Empty, Full, Programmable Almost Empty, and Programmable Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty+7 and Full-7. The flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full, and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.5 CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4282/92-10 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Active Power Supply Current (ICC) (mA) Commercial Industrial 100 8 10 3 0.5 8 40 45 7C4282/92-15 66.7 10 15 4 1 10 40 7C4282/92-25 40 15 25 6 1 15 40
CY7C4282 Density Package 64k x 9 64-pin 10x10 STQFP
CY7C4292 128k x 9 64-pin 10x10 STQFP
D1 D0 N/C N/C N/C VCC PAF/XO PAE N/C N/C N/C N/C N/C GND REN RCLK
2
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................... -65C to +150C Ambient Temperature with Power Applied .................................................... -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ..............................................-0.5V to VCC+0.5V DC Input Voltage .........................................-0.5V to V CC +0.5V Output Current into Outputs (LOW) ............................. 20 mA
CY7C4282 CY7C4292
Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial[1] Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Note: 1. TA is the "instant on" case temperature.
Pin Definitions
Signal Name D0 - 8 Q0 - 8 WEN REN WCLK RCLK EF FF PAE PAF/XO Description Data Inputs Data Outputs Write Enable Read Enable Write Clock Read Clock Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full/ Expansion Output First Load/ Retransmit I/O I O I I I I O O O O Data Inputs for 9-bit bus Data Outputs for 9-bit bus The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH. Enables the device for Read operation. REN must be asserted LOW to allow a read operation. The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is LOW, RCLK reads data out of the programmable flag-offset register. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. PAE is synchronized to RCLK. Dual-Mode Pin: Cascaded - Connected to XI of next device. Not Cascaded - When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is synchronized to WCLK. Dual-Mode Pin: Cascaded - The first device in the daisy chain will have FL tied to V SS; all other devices will have FL tied to V CC. In standard mode or width expansion, FL is tied to VSS on all devices. Not Cascaded - Retransmit function is available in stand-alone mode by strobing RT. Dual-Mode Pin: Cascaded - Connected to XO of previous device. Not Cascaded - LD is used to write or read the programmable flag offset registers. LD must be asserted low during reset to enable standalone or width expansion operation. If programmable offset register access is not required, LD can be tied to RS directly. When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. Description
FL/RT
I
XI/LD
Expansion Input/Load
I
OE RS
Output Enable Reset
I I
3
PRELIMINARY
Electrical Characteristics Over the Operating Range[2]
CY7C4282 CY7C4292
7C4282/92-10 7C4282/92-15 7C4282/92-25 Parameter VOH VOL VIH VIL IIX IOZL IOZH ICC1[3] ISB[4] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC = Max. OE > VIH, VSS < VO< VCC Com'l Ind Com'l Ind Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.5 -10 -10 Min. 2.4 0.4 VCC 0.8 +10 +10 40 45 2 2 2 2 2.0 -0.5 -10 -10 Max. Min. 2.4 0.4 VCC 0.8 +10 +10 40 2.0 -0.5 -10 -10 Max. Min. 2.4 0.4 VCC 0.8 +10 +10 40 Max. Unit V V V V A A mA mA mA mA
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 5 7 Unit pF pF
AC Test Loads and Waveforms[6, 7]
R11.1K 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THE VENIN EQUIVALENT 410 OUTPUT R2 680 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10% 3 ns
4282-5
4282-4
1.91V
Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20Mhz, while data inputs switch at 10 MHz. Outputs are unloaded. 4. All inputs = VCC - 0.2V, except WCLK and RCLK (which are switching at frequency = 0 MHz). All outputs are unloaded. 5. Tested initially and after any design or process changes that may affect these parameters. 6. CL = 30 pF for all AC parameters except for tOHZ. 7. CL = 5 pF for tOHZ.
4
PRELIMINARY
Switching Characteristics Over the Operating Range
7C4282/92-10 Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tPRT tRTR tOLZ tOE tOHZ tWFF tREF tPAF tPAE tSKEW1 tSKEW2 Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-Up Time Data Hold Time Enable Set-Up Time Enable Hold Time Reset Pulse Width
[8]
CY7C4282 CY7C4292
7C4282/92-15 Min. 2 15 6 6 4 1 4 1 15 10 10 Max. 66.7 10
7C4282/92-25 Min. 2 25 10 10 6 1 6 1 25 15 15 Max. 40 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns 25 60 90 0 ns ns ns ns 12 12 15 15 15 15 10 18 ns ns ns ns ns ns ns ns
Description Clock Cycle Frequency
Min. 2 10 4.5 4.5 3 0.5 3 0.5 10 8 8
Max. 100 8
Reset Set-Up Time Reset Recovery Time Reset to Flag and Output Time Retransmit Pulse Width Retransmit Recovery Time Output Enable to Output in Low Z Output Enable to Output Valid Output Enable to Output in High Z Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Full Flag Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag Skew Time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag
[9] [9]
10 60 90 0 3 3 7 7 8 8 8 8 5 10 6 15 60 90 0 3 3
15
8 8 10 10 10 10
3 3
Notes: 8. Pulse widths less than minimum values are not allowed. 9. Values guaranteed by design, not currently tested.
5
PRELIMINARY
Switching Waveforms
Write Cycle Timing
tCLK tCLKH WCLK tDS D0 -D17 tENS WEN tWFF FF tSKEW1 [10] RCLK tWFF tENH
NO OPERATION
CY7C4282 CY7C4292
tCLKL
tDH
REN
4282-6
Read Cycle Timing
tCLK tCLKH RCLK tENS REN tREF EF tA Q0 -Q17 tOLZ tOE OE tSKEW1 [11] WCLK
VALID DATA
tCLKL
tENH
NO OPERATION
tREF
tOHZ
WEN
4282-7
Notes: 10. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 11. tSKEW1 is also the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
6
PRELIMINARY
Switching Waveforms (continued)
Reset Timing [12]
tRSS LD
[13]
CY7C4282 CY7C4292
tRS RS tRSR REN, WEN tRSF EF,PAE tRSF FF,PAF tRSF Q0 - Q8 OE=0
4282-8
OE=1
[14]
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK tDS D0 -D8 tENS WEN tSKEW1 RCLK tREF EF tFRL
[15]
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
REN tA Q0 -Q8 tOLZ tOE OE
4282-9
tA D0
[16]
D1
Notes: 12. The clocks (RCLK, WCLK) can be free-running during reset. 13. For standalone or width expansion configuration only. 14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1. 15. When t SKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 16. The first word is available the cycle after EF goes HIGH, always.
7
PRELIMINARY
Switching Waveforms (continued)
Empty Flag Timing
WCLK tDS D0 -D8 tENS WEN tFRL RCLK tSKEW1 EF REN LOW OE tA Q0 -Q8 DATA IN OUTPUT REGISTER DATA READ tREF tREF tSKEW2
[15]
CY7C4282 CY7C4292
tDS DATA WRITE 1 tENH tENS tFRL
[15]
DATA WRITE 2 tENH
tREF
4282-10
Full Flag Timing
WCLK tSKEW1[10] D0 -D8
NO WRITE
NO WRITE
tDS DATA WRITE tWFF
tSKEW1
[10]
DATA WRITE
tWFF
tWFF
FF
WEN
RCLK tENH REN tENS tENS tENH
OE
LOW tA tA DATA READ NEXT DATA READ
Q0 -Q8
DATA IN OUTPUT REGISTER
4282-11
8
PRELIMINARY
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKH WCLK tENS tENH WEN tCLKL
CY7C4282 CY7C4292
PAE tSKEW2 RCLK
[17]
Note 18 tPAE
N + 1 WORDS IN FIFO
Note 19 t PAE
tENS REN
tENS tENH
Programmable Almost Full Flag Timing
tCLKH WCLK tENS tENH WEN tPAF PAF FULL - (M+1)WORDS IN FIFO FULL - M WORDS IN FIFO [21] tSKEW2 [22] tPAF tCLKL Note 20
RCLK tENS REN
4282-13
tENS tENH
Notes: 17. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 18. PAE offset= n. 19. If a read is preformed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW 20. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when PAF goes LOW. 21. 16,384 - m words for CY7C4282, 32,768 - m words for CY4292. 22. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
9
PRELIMINARY
Switching Waveforms (continued)
Write Programmable Registers
tCLK tCLKH WCLK tENS LD tENS WEN tDS D0 -D8 PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB tDH tENH tCLKL
CY7C4282 CY7C4292
PAF OFFSET MSB
4282-14
Read Programmable Registers
tCLK tCLKH RCLK LD tENS tENH tCLKL
tENS REN tA Q0 -Q15 UNKNOWN PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB
4282-15
PAF OFFSET MSB
10
PRELIMINARY
[23, 24, 25]
CY7C4282 CY7C4292
Retransmit Timing
FL/RT
tPRT tRTR REN/WEN
EF/FF
4282V-16
Notes: 23. Clocks are free running in this case. 24. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 25. For the synchronous PAE and PAF flags, an appropriate clock cycle is necessary after tRTR to update these flags.
11
PRELIMINARY
Architecture
The CY7C4282/92 consists of an array of 64K to 128K words of 9 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).
64K x9 8 7
Empty Offset (LSB) Reg. Default Value = 007h
CY7C4282 CY7C4292
128K x9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
0
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0-8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW. During reset of the FIFO, the state of the XI/LD pin determines if depth expansion operation is used. For depth expansion operation, XI/LD is tied to XO of the next device. See "Depth Expansion Configuration" and Figure 3. For Standalone or width expansion configuration, the XI/LD pin must be asserted low during reset. There is a 0-ns hold time requirement for the XI/LD configuration at the RS deassertion edge. This allows the user to tie XI/LD to RS directly for applications that do not require access to the flag offset registers.
8
7
0
(MSB) Default Value = 000h
8
0
(MSB) Default Value = 000h
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
0
(MSB) Default Value = 000h
8
0
(MSB) Default Value = 000h
4282-16
Figure 1. Offset Register Location and Default Values It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the LD input HIGH, the FIFO is returned to normal read and write operation. The next time LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when LD is LOW and REN is LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers. Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. Table 1. Writing the Offset Registers LD 0 WEN 0 WCLK [26] Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Into FIFO
FIFO Operation
When the WEN is asserted LOW and FF is HIGH, data present on the D0-8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN is asserted LOW and EF is HIGH, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of RCLK while REN is active. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0-8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Q0-8 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-8 outputs even after additional reads occur.
Programming
When LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, LD can be used to access the four 9-bit offset registers contained in the CY7C4282/92 for writing or reading data to these registers. When the device is configured for programmable flags and both LD and WEN are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset most significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when LD and WEN are LOW. The fifth LOW-to-HIGH transition of WCLK while LD and WEN are LOW writes data to the empty LSB register again. Figure 1 shows the registers sizes and default values for the various device types. 0 1 1 0
1
1
No Operation
Note: 26. The same selection sequence applies to reading from the registers. REN is enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
12
PRELIMINARY
The number formed by the empty offset least significant bit register and empty offset most significant bit register is referred to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF PAF is synchronized to the . LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4282 (64K-m) and CY7C4292 (128K-m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m.
CY7C4282 CY7C4292
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C4282/92 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags.
Flag Operation
The CY7C4282/92 devices provide four flag pins to indicate the condition of the FIFO contents. All flags operate synchronously.
Table 2. Status Flags Number of Words in FIFO CY7C4282 0 1 to n
[27]
CY7C4292 0 1 to n
[27]
FF H H H H L
PAF H H H L L
PAE L L H H H
EF L H H H H
(n+1) to (65536 - (m+1)) (65536 - m) 65536
Notes: 27. n = Empty Offset (n=7 default value). 28. m = Full Offset (m=7 default value).
(n+1) to (131072 - (m+1)) (131072 - m) 131072
[28]
[28]
to 65535
to 131071
13
PRELIMINARY
Retransmit
The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the stand-alone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incriminated until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are
CY7C4282 CY7C4292
transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
Width Expansion Configuration
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C4282/92. Any word width can be attained by adding additional CY7C4282/92. When the CY7C4282/92 is in a Width Expansion Configuration, the Read Enable (REN) control input can be grounded (See Figure 2). In this configuration, the Load (LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
RESET (RS) DATA IN (D) 18
9 9
RESET (RS)
READ CLOCK (RCLK) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) EMPTY FLAG (EF) FF FULL FLAG (FF)
9
READ ENABLE (REN) OUTPUT ENABLE (OE) PROGRAMMABLE (PAF)
CY7C4282/92
CY7C4282/92
EF
FF
EF
9
DATA OUT (Q)
18
FIRST LOAD (FL) EXPANSION IN (XI)
FIRST LOAD (FL) EXPANSION IN (XI)
4282-17
Figure 2. Block Diagram of 64Kx9/128Kx9 One Meg Deep Sync FIFO Memory Used in a Width Expansion Configuration
14
PRELIMINARY
Depth Expansion Configuration
The CY7C4282/92 can easily be adapted to applications requiring more than 64K/128K words of buffering. Figure 3 shows Depth Expansion using three CY7C4282/92s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state.
CY7C4282 CY7C4292
3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. 4. EF and FF composite flags are created by O-Ring together each individual respective flag.
XO RCLK WCLK REN WEN OE RS 7C4282 D 7C4292 Q VCC FL FF XI EF
DATA IN (D) VCC
XO RCLK WCLK REN WEN OE RS 7C4282 D 7C4292 Q
DATA OUT (Q)
FL FF XI
EF
WRITECLOCK (WCLK) WCLK WRITEENABLE (WEN) WEN RESET (RS)
XO RCLK REN
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUTENABLE (OE)
RS 7C4282 OE 7C4292 Q D FF
FF FL FIRST LOAD (FL) XI
EF
EF
4282-25
Figure 3. Block Diagram of 64Kx9/128Kx9 One Meg Deep Sync FIFO Memory with Programmable Flags used in Depth Expansion Configuration
15
PRELIMINARY
Ordering Information
64K x 9 Deep Sync FIFO Speed (ns) 10 15 25 Ordering Code CY7C4282-10ASC CY7C4282-10ASI CY7C4282-15ASC CY7C4282-25ASC Package Name A64 A64 A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Industrial Commercial Commercial
CY7C4282 CY7C4292
128K x 9 Deep Sync FIFO Speed (ns) 10 15 25 Ordering Code CY7C4292-10ASC CY7C4292-10ASI CY7C4292-15ASC CY7C4292-25ASC Package Name A64 A64 A64 A64 Package Type 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack Operating Range Commercial Industrial Commercial Commercial
Document #: 38-00594-A
Package Diagram
64-Pin Thin Quad Flat Pack A64
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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